Many semiconductor non-volatile memory arrays require a relatively high voltage for programming and erasing operations. During manufacture of the non-volatile memory arrays, high voltage tolerant transistors that can withstand, for example, the relatively high programming and erase voltages are implemented at the same time as the array. In a non-volatile memory array that relies on nanocrystals for charge storage, the charge storage layer is formed prior to the formation of the high voltage transistor gate oxide. The subsequent formation of oxide layers may cause further oxidation of the insulating layers. Further oxidation in the non-volatile device may lead to an increase in the tunnel oxide thickness. Also, further oxidation may cause the nanocrystals to oxidize and shrink. Changing the charge storage layer may lead to the need for higher program and erase voltages. Also, changing the charge storage layer may lead to an undesirable change in program and erase threshold voltages.
Therefore, there is a need for a non-volatile memory device having an accurately controlled charge storage region while also reducing the steps needed to manufacture the device.